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Description Examples by SFL

Examples in PARTHENON release package

test.sfl -> synthesized circuit diagram (PS file) (Image)

sevenseg.sfl -> synthesized circuit diagram (PS file) (Image)

maj7.sfl -> synthesized circuit diagram (PS file) (Image)

cpu.sfl -> synthesized circuit diagram (multi-page) (PS file) (Image), synthesized circuit diagram (single page) (PS file) (Image)

Example of FDDP

Here is the SFL description of 32-bit RISC-type processor FDDP (Four-Day-Designed Processor) which employed a DLX-compatible instruction subset and a 5-stage pipelined architecture.

It took only two days to complete the behavior design and to make the test data. One day was needed to conduct functional verification and make architectural improvements using SECONDS. Another day was required for synthesizing the logic circuits from the behavior design. All of the circuits of this processor were synthesized within one hour of CPU time using an HP/Apollo DN10010 workstation.

new.sfl new.cir -> ->

Example of SFLCPU

Design examples of the simple microprocessor SFLCPU written in the following proceeding.

A. Nagoya, Y. Nakamura and R. Nomura: "Microprocessor Architecture Design Using High-Level Synthesis System," Proc. of International Symposium on Logic Synthesis and Microprocessor Architecture (ISKIT '92), pp. 55-59, Jul. 1992.

SFLCPU cannot be designed using streamlined control such as that employed in RISC processor design. The following processor design steps were taken during the SFLCPU architecture refining process.

(a) SFLCPU_S: A simple state machine model.
(b) SFLCPU_P: An advanced instruction fetch control mechanism was introduced into the model.
(c) SFLCPU_H: Harvard architecture, which provides two memory access paths - one for the instruction and the other for the operand - was introduced.
(d) SFLCPU_H2: The band width for the instruction memory was widened to achieve a one-cycle fetch mechanism for every instruction.
(e) SFLCPU_1T: A 3-stage pipeline control model was introduced to run three instructions simultaneously.
(f) SFLCPU_1TV: A new pipeline control concept was introduced to reduce pipeline hazards.

The above architecture refining process was carried out within 2 person-days. The behavioral simulator SECONDS makes it easy for the designer to try out his ideas and improve his design through quantitative performance estimation.

This file contains 6 types of SFL description and simulation scripts for them.

sflcpu.tgz (5,751 Byte)

Example of KUE-CHIP2

here (in Japanese)

Examples by PARTHENON users

here (in Japanese)