/*
 *	alu16.sfl
 */

module alu16 {

submod_type add16 {
	input		a<16>, b<16>, ci;
	output		y<16>, co;
	instrin		enable;
	instr_arg	enable(a, b, ci);
}

submod_type brlsft16 {
	input		shift;
	input		right;
	input		sign;
	input		a<16>, b<4>;
	output		y<16>;
	instrin		enable;
	instr_arg	enable(shift, right, sign, a, b);
}


input		a<16>, b<16>;
output		y<16>;
instrin		sa,  sb;
instrin		and, or,  xor, not;
instrin		add, sub;
instrin		sll, srl, sra;
instrin		rol, ror;
instrin		sgt, slt, seq;
instrin		sge, sle, sne;		/* not slt, not sgt, not seq */
instrin		ldl, ldh;

instrself	iseq;


add16		ADD;			/* 16bit adder	*/
brlsft16	SFT;			/* 16bit shiter	*/

tmp		tmp<16>;
tmp		neq;


instruct sa	y = a;
instruct sb	y = b;

instruct and	y = a & b;
instruct or	y = a | b;
instruct xor	y = a @ b;
instruct not	y = ^a;

instruct add	y = ADD.enable(a, b, 0b0).y;
instruct sub	y = ADD.enable(a, ^b, 0b1).y;

instruct sll	y = SFT.enable(0b1, 0b0, 0b0, a, b<3:0>).y;
instruct srl	y = SFT.enable(0b1, 0b1, 0b0, a, b<3:0>).y;
instruct sra	y = SFT.enable(0b1, 0b1, 0b1, a, b<3:0>).y;
instruct rol	y = SFT.enable(0b0, 0b0, 0b0, a, b<3:0>).y;
instruct ror	y = SFT.enable(0b0, 0b1, 0b0, a, b<3:0>).y;


instruct sgt alt {
ADD.enable(^a, b, 0b1).co:
	y = 0x0000;
else:
	y = 0xFFFF;
}

instruct sle alt {
ADD.enable(^a, b, 0b1).co:
	y = 0xFFFF;
else:
	y = 0x0000;
}

instruct slt alt {
ADD.enable(a, ^b, 0b1).co:
	y = 0x0000;
else:
	y = 0xFFFF;
}

instruct sge alt {
ADD.enable(a, ^b, 0b1).co:
	y = 0xFFFF;
else:
	y = 0x0000;
}

instruct seq par {
	iseq();
	alt {
	neq:
		y = 0x0000;
	else:
		y = 0xFFFF;
	}
}

instruct sne par {
	iseq();
	alt {
	neq:
		y = 0xFFFF;
	else:
		y = 0x0000;
	}
}

instruct ldl	y = b<7>||b<7>||b<7>||b<7>||b<7>||b<7>||b<7>||b<7>||b<7:0>;
instruct ldh	y = b<7:0> || a<7:0>;

instruct iseq par {
	tmp	= a @ b;
	neq	= tmp<15> | tmp<14> | tmp<13> | tmp<12> | 
		  tmp<11> | tmp<10> | tmp<9>  | tmp<8>  | 
		  tmp<7>  | tmp<6>  | tmp<5>  | tmp<4>  |
		  tmp<3>  | tmp<2>  | tmp<1>  | tmp<0>;
}

} /* alu16 */