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To begin with, you may have reservations about a CAD that has been developed by a company like NTT that has no production plants. This may sound paradoxical, but the very fact that NTT has no production plants is what prompted us to research and develop the PARTHENON system.
In 1972, those who were to develop PARTHENON were engaged in the research and development of a large-scale general-purpose computer named DIPS (Denden-kosha Information Processing System), determined to make it the world's number one computer, in cooperation with NEC Corp., Hitachi Ltd., and FUJITSU Ltd. When the first model, DIPS-1, was already in operation, the IBM 370 was introduced, an epoch-making system introducing semiconductor memory. To compete with it, the designers in NTT undertook the development for the central processing unit (CPU) of DIPS-11.
In this cooperative project, we NTT engineers were responsible for the examination of the so-called "system", and for providing the "logical specifications/physical specifications" to the manufacturers. In other words, we were responsible for the architecture of the device. Our job was to determine the functions, capabilities, and costs of the CPU, and to determine the basic system of the processor, including the specifications of instructions, to satisfy these conditions. An example of how such examination of a "system" is performed is described below, taking the part we examined as an example.
For example, to use the cache memory (hereinafter referred to as "cache") system in a virtual storage system, we had to make a comprehensive, however brief, study on the following different issues. (For details, please refer to "Effective Design Method for ULSIs" by NAKAMURA and ONO, Ohmsha Ltd., 1994.)
As is well known, the cache system keeps copies of parts of low-speed-large-capacity main memory (hereinafter referred to as MEM) in high-speed-small-capacity memory in the CPU in order to realize a virtual high-speed-large-capacity memory system. The key to this system is how to increase the frequency at which the necessary data (indicated by the logical address) is found in the cache; in other words, how to reduce the Not-Found-Probability (NFP).
The following shows what main system issues were studied to determine the specifications.
In system design, both qualitative and quantitative examinations are required. For example, while item (3) mainly requires only the logical thinking of how to ensure the data consistency between the cache and the MEM, items (1), (2) and (4) absolutely require quantitative examination to grasp how much each alternative is superior to others in performance or usefulness.
Conventionally, dedicated simulators were developed or general-purpose simulators, such as GPSS, were used for quantitative evaluation of models, regarding, for example, influences of sector size, block size or cache size on the CPU performance. These methods have the following problems:
This gap (discontinuity) between the system design and the manufacturing design was tremendously irritating for us system designers at NTT. It was because the valuable outcome of the above-mentioned system design was not efficiently linked to manufacturing design and was not to be used as actual design resources. Therefore, as a matter of course, we sought for a tool both effective for system design and architecture design and making the work executed using such a tool be directly linked to the manufacturing design.
In the absence of such a tool, we developed PARTHENON. Manufacturers might not be aware of the problems involved which we as system designers at NTT had in mind, since, for them, the production of circuit diagrams is necessary for manufacturing anyway.
Again, no matter how earnestly we sought for "the highest design method effectively linked to manufacturing design", what we found as the practical "highest" was "the conventional logic design method by circuit diagram generation". Surprisingly, the situation would be essentially the same at present, twenty years later, if PARTHENON did not exist.
Against such background, the research of PARTHENON was started based on a research program laid down after six months of preliminary examinations and approved on January 6, 1981. The tool this program aims at was to support the work of system designers, a sharp contrast to the conventional CAD, i.e., "LSI-DA", which is created to support the work of component designers. The program was aptly named Research Program for "System DA." The tool developed in the program had been called "system DA" and used within NTT, but was renamed PARTHENON in 1990 on the occasion of its disclosure to the public.
PARTHENON enabled system design and architecture design through programming parallel operation of hardware. In conventional methods, a breadboard had to be prepared, and then measurement had to be made with hardware and software monitors before characteristics and evaluation data were obtained. With PARTHENON now available, such data can be obtained easily and with high accuracy during the design stage by simulation and logic synthesis using the information of real cells. System designers who have experience in design and development of large-scale systems may well understand how much value such capability brings.
Hardware technology has advanced remarkably since we started research for PARTHENON sixteen years ago. Today, microprocessor chips normally include more than100 K gates. Thus, the urgent requirement for a higher CAD for system design which motivated the development of PARTHENON is not specific to NTT but is more relevant than ever for everyone in the industry. The price reduction of workstations allowing each designer to have his own machine and the advancement in performance of personal computers up to the level of workstations has enabled the age to catch up with the designing culture of PARTHENON and gives PARTHENON value as a practical technology.
Hereby, the world of higher parallel logic, algorithm, and architecture is completely separated from the world dominated by physical conditions at gate or lower levels. Thus, system designers were disengaged from the world of lower-level thinking where gate logic circuit design such as multi-phase clocks or asynchronization are thought to be the targets of design ideas, into the world of higher-level thinking which targets parallel architectures.
For this purpose, we decided to feature SFL as the parallel behavior description language assuming the use for clocks and to make PARTHENON synthesize only synchronous circuits. At first glance, it may strike you that the architecture of SFL/PARTHENON has rigorous limitations as a CAD. But, we hope the above explanation will lead you to understand that this is the only positive and aggressive solution to realize a truly practical CAD for system design.
You may think that you have experienced something similar or have heard of a similar story. Yes, in the late 1960s, there were those arrogant enough to say, "High-level languages and compilers cannot produce serious software. Look at my skillful job with assemblers and machine languages." Nowadays, we cannot think of software development without high-level languages such as C or FORTRAN. In the wake of this software design revolution, the age of renovation has finally come to hardware design as well, in which the use of high-level algorithm languages is the mainstream. We believe PARTHENON, which truly supports system design, can be a key to usher in such an age.
Logic synthesis tools other than PARTHENON are rarely used for designing a whole ASIC. They are used for synthesis of merely parts of an ASIC, such as combinatorial logic or control logic. The fact that only PARTHENON reaches the practical level to realize the logic synthesis of the entire processor unmistakably demonstrates the superiority of PARTHENON's design concept.
In discussing high-level design languages, SFL is often picked up along with Verilog, VHDL, and UDL/I. For example, the special issue for hardware description languages of the journal of the Information Processing Society of Japan, published in November 1992, reported the use of these four languages in comparative studies on designing the same processor (KUE-CHIP (Kyoto University Education CHIP)). It reported that SFL used in combination with PARTHENON was the only technology among them that had no practical problems.
For reference purposes, the dates when the languages were developed are shown. Please note that the three other languages did not exist for five years after the unveiling of SFL basic specifications. Such facts notwithstanding, it is unfortunately true that PARTHENON's concept has not prevailed.
It is extremely difficult for the present VHDL and Verilog-HDL, that are constructed on an asynchronous paradigm, to realize the advantages of PARTHENON. If their specifications are to be modified one way or another to accommodate the advantages of PARTHENON, they will become too clumsy to work with. Although we are not going to give detailed explanations on these points, SFL should not be discussed at the same level with VHDL, as it is clearly positioned at a higher level.
Although having faced various difficulties, PARTHENON is steadily contributing to society. In the first place, several companies in the industry including NTT are increasingly using PARTHENON. The evidence of significant reduction in man-hours for design has prompted its application to the most advanced ASIC. Among such applications, its uses on the designs of the vector processor for super high-definition image processing by NTT and on the designs of the MUSE decoder by Sanyo Electric Co., Ltd. were reported. It is also effective for relatively small LSI design at smaller design houses. Design examples often appear on such monthly journals as "Transistor Technologies" and "Interface," as you already know.
In the academic field, many educational organizations including universities all over Japan and technical colleges, such as Toyota National College of Technology, are using PARTHENON for research, design, and education of hardware with advanced architecture such as the next generation DSP (Digital Signal Processor). As of May 1995, a total of 372 systems of PARTHENON were used by seventy-six teachers nationwide.
In November 1992, the PARTHENON Technical Society was established by these teachers and others. So far, six seminars have been held for presentation of study results and for mutual utilization of design resources. The second meeting held on April 5, 1993 was cosponsored by IEEE Tokyo Chapter. Furthermore, we are pleased that many excellent designs were submitted to the first and second ASIC design contests held by the PARTHENON Technical Society.
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