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Since SFL is applied to a "synchronous circuit with a single-phase clock", the state of a stage consisting of register, memory or storage elements, the state of a task and a segment return state change in synchronization with clock pulses. Although we have said that SFL is applied to a "synchronous circuit with a single-phase clock," this was to facilitate understanding. In reality, SFL is applicable to registers with a master slave latch updated by a master clock and a slave clock. The point is that all registers should be updated at the same time by a certain event.
In SFL, power-on reset is executed and stages are set to the initial states, and registers indicating tasks are reset before the arrival of the first clock pulse. Registers are, depending on their type, in one of the three states: set, reset or "unknown". Memory is in the state of unknown.
SFL provides no specific format to handle system reset or unit reset. Various types of reset must be designed and described as part of a normal operation. All resets are synchronous.
• Machine cycle
A machine cycle is the period from one clock pulse to the next. It would be simpler to understand that a machine cycle does not include clocks themselves. Think of the clock pulse as simply an event defining machine cycle boundaries.
Example of describing a stage operation
Control terminal and stage operations are described with the machine cycle as a minimum unit of time. Relative timing within a machine cycle is not specified. For example:
state st1 par {
goto st2 ;
out = counter ;
counter := in ;
do() ;
}
indicates that, "where a stage is in 'st1' state, the following four operations are executed in parallel within a machine cycle regardless of the order in which these statements appear."
goto st2 ;where "par" denotes a key word for putting multiple operations in parallel, "st2" another state, "out" a data output terminal, "counter" a register name, "in" a data input terminal, and "do" the control output terminal name.out = counter ;
counter := in ;
do() ;
Writing data in register "counter:=in;" updates the register value only at the clock pulse. The updated value can be referenced only in the next machine cycle or later. Register values are retained until the next update.
Since the stage state is retained in the state register, the state transition of "goto st2;" takes effect at the next clock pulse. The stage adopts the updated state in the next machine cycle and remains unchanged until it is further updated.
On the other hand, the output to data terminal of "out=counter;" immediately updates the data terminal value. For example, if "a", "b" and "c" are all data terminals,
par { a = b;
b = c;
c = 0x4; /* 0x4 indicates 4 in hexadecimal */
}
sets each of "a", "b" and "c" to 4 in this machine cycle. Also, data terminal values are not retained over multiple machine cycles.
So far we have seen that the update timing of registers and states is different from data update timing of data terminals. To put this another way, the difference is whether the element is a "storage element like a register" or a "mere terminal." The same is true for the activation of subjects of operation (stage and control terminal). The "stage task set/reset takes effect in the next machine cycle" but "control terminal activation is immediately effective." Therefore, control terminal activation of "do();" in the first example above takes effect immediately in this machine cycle.
Example of describing multiple operations
Since writing to register and memory, state transition, and task set/reset are all carried out at the timing of clock arrival and output of values to data terminals and control terminal activation are carried out immediately, multiple operations within a machine cycle produce the same results irrespective of the order in which these statements appear. For example:
state st1 any {
flg : if ( do().result ) reg2 := in ;
else : reg1 := in ;
}
instruct do par {
result = 0b1 ;
}
indicates the following. Where a stage is in "st1" state, if flg is "1", the following is executed:
if ( do ().result ) reg2 := in ;
Otherwise, the following is executed:
reg1 := in ;
When the control terminal "do" is activated, the following is executed:
result = 0b1 ;
The expression
if ( do().result ) reg2 := in ;
means that, if "do ().result" is "1", then the following is executed.
reg2 := in ;
The expression
do().result
means that control terminal "do" is activated without any argument and the result is put in "result". The key words "any" and "if" are described in Section 3.10.
If "flg" happens to be "0", control terminal "do" is not executed from a logical point of view, and the "result" value becomes "no-value". However, since the conditional referencing of "if ( do().result )" is not executed either, no error occurs, and only "reg1 :=in;" is executed. "The rule of disallowing conditional reference to elements without values" is explained in Section 3.10.
In a real circuit, if "flg" is an output from a combinational circuit, its value may fluctuate between "0" or "1" until it settles to a stable state. As a result, the value of the control terminal "do," the value of "result", and the signal written into register "reg2" may also oscillate between "1" or "0". It is the principle of the SFL model that "writing in registers occurs after all combinatorial logic is settled in a stable state." If a circuit meets this SFL model, its real behavior should be the same as its logical behavior.
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