Module Structure
The previous section looked at elements of a module in terms of whether it is the subject or object of operation. In this section, we classify them from another perspective to give a wider picture of elements (Table 3.2). Module description can be divided into the following:
External terminals can be classified into control terminals and data terminals according to whether they are the subject or object of operation.
External control terminals can be classified into control input terminals, which are controlled from outside, and control output terminals, which control the outside world.
External data terminals can be classified into data input terminals, which receive data from outside, data output terminals, which send data to the outside world, and bidirectional data terminals, which send and receive data.
Component elements are inside a module and can be classified into internal control terminals, stages, internal data terminals, registers, memories and sub-modules. Internal control terminals and stages are subjects of operation while internal data terminals, registers, and memories are objects of operation. A sub-module can be either a subject or object of operation depending on the type of external terminals it has.
<Table 3.2> External terminals and component elements
Definition of component elements, and basic format
External terminals and component elements (except for stages) are defined in the following format.
TypeNname InstanceName {, InstanceName};
where the TypeName is either a built-in type name or other module name.
For example,
These define respectively: 1-bit register by the name of "flg", 32-bit register by the name of "pc" and 1024-word, 32-bit memory by the name of "array". In this way, the number of bit width is specified with <number>, and the number of words is specified with [number]. The number of words can be specified only when the type name is mem.reg flg ;
reg pc<32> ;
mem array[1024]<32> ;
Definition of four types of internal data terminal
There are four type names for defining internal data terminals: "sel", "bus", "sel_v" and "bus_v". Let us see what they are. The type names, "sel" and "bus", signify the following:
sel: Selector by logic gateIf internal data terminals are defined with these type names, the logic synthesis of SFLEXP performs logic minimization separately on either side of the internal data terminal. That is, the internal data terminal is contained in the logic synthesis result of SFLEXP.bus: Selector by 3-state
If "sel_v" or "bus_v" are specified, where possible the whole logic including the internal data terminals is minimized at the time of logic synthesis with SFLEXP. That is, these terminals themselves are subject to logic minimization. Noted that "v" stands for "virtual". If logic minimization for the entire logic is difficult, the result is the same as that using "sel" and "bus".
Definition of register and memory
There are three type names for defining a register depending on how the initial value of the register is handled:
reg : Register whose content is neither set nor reset at power-onMemory ("mem") can be used only in a functional circuit. The following constraints also apply.reg_ws : Register whose content is set at power-on (with set)
reg_wr : Register whose content is reset at power-on (with reset)
The number of words in memory can be up to 227 (134217728) and must be in powers of 2. The number of words cannot be omitted. A memory address starts at 0.
The number of bit width of a register, memory or data terminal ranges from 1 to 256. The default number of bit width is 1.
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