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• Operations and unit operations
The format expressing an operation within one machine cycle is called an operation. Component elements such as "par", "alt", "any", "if" and "else" are used to express parallelism and the hierarchical relationships between conditions. An individual operation is called a unit operation.
A unit operation can be an operation. Two or more operations can become an operation when they are expressed as follows:
par {
UnitOperation1
UnitOperation2
}
• Conditional control
The simplest format for conditional control is
if (Condition) Operation
The number of bit width of the condition expression must be 1. The operation is executed if the value of the conditional expression is "1". If an operation is to be conditionally controlled, the condition must not be "unknown". If it can become "unknown", the SFL description is incorrect, and the processing system will not operate correctly. If an "unknown" condition is encountered during simulation, the simulator will report an error.
Multiple operation with conditions
The key word "any" can aggregate a number of operations with conditions. For example:
any {
Condition1 :Operation1;
Condition2 :Operation2;
Condition3 :Operation3;
else :Operation4;
}
If Condition1 is true, Operation1 is executed. If Condition2 is true, Operation2 is executed. If Condition3 is true, Operation3 is executed. If Condition1, Condition2 and Condition3 are all true, Operation1, Operation2 and Operation3 are all executed. Operation 4 is executed only if none of Condition1, Condition2 or Condition3 is true.
" if (Condition) Operation " is the same as " any {Condition: Operation} ".
Operations with multiple priority conditions
The key word "alt" can aggregate a number of operations with priority conditions. For example:
alt {
Condition1 :Operation1;
Condition2 :Operation2;
Condition3 :Operation3;
else :Operation4;
}
If Condition1 is true, Operation1 is executed. If Condition2 is true but Condition1 false, Operation2 is executed. If Condition3 is true but Condition1 and Condition2 are false, Operation3 is executed. If none of Condition1, Condition2 or Condition3 is true, Operation4 is executed.
Nesting of conditions
"par", "any" and "alt" can be nested. For example:
state st1 any {
flg : par {
counter := in ;
goto st2 ;
any {
counter<0> : out = in ;
else : out = counter ;
}
}
}
In the above example, "any {...}" is defined as an operation of state "st1". The above means that "in the machine cycle where the stage is in state 'st1', 'counter:=in;' and 'goto st2;' are executed if 'flg' is '1'; furthermore 'out=in;' is executed if bit 0 (the least significant bit) of 'counter' is '1'; otherwise, 'out=counter;' is executed."
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