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SFL and PARTHENON have features that are markedly different from those of other logic synthesis systems. These features are described below:
Although at first glance this framework may look restrictive regarding the circuits that can be designed, in reality it is not. On the contrary, these features provide an appropriate framework for the actual design of large-scale logic circuits. They were conceived as a result of the simultaneous research and development of the hardware description language SFL, the simulator and synthesis systems. The SFL language specifications were defined with a view to executing all of the following functions effectively and consistently:
Though the logic synthesis obtained from the RTL procedure description in PARTHENON cannot be said to correspond to the term "High-Level Synthesis" as it is understood in the field of CAD research, it can be called "High-Level Synthesis" in the sense that it synthesizes the entire system from a procedure description.
The workstation version of PARTHENON has been applied not only to the ASIC designs of commercial products and for research and trial purposes in the industry, but also for research and educational purposes in universities and technical colleges. PARTHENON's compatibility with FPGA mapping tools has been proven in the case of work with Altera's FLEX series. PARTHENON users have organized the PARTHENON Technical Society to promote information exchange and discussion, and provide short study courses regarding the use of PARTHENON. The users of the PARTHENON/CQ version are encouraged to consider the introduction of the PARTHENON workstation version as a larger-scale design system .
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