What is the PARTHENON System?

PARTHENON (Parallel Architecture Refiner Theorized by NTT Original Concept) is an electronic design automation (EDA) system developed entirely by NTT laboratories. Along with this system, the hardware description language for PARTHENON, called SFL (Structured Function Description Language), was also developed by NTT.

Since the early 1980s, NTT Electrical Communication Laboratories have been researching and developing SFL, its simulator, and logic synthesis systems. After developing and evaluating a prototype at the end of the 1980s, NTT disclosed the language specifications for SFL to the public, and commenced sale of a commercial system under the name of "PARTHENON."

The latest version of PARTHENON, version 2.3, which runs on SPARCstation or HP/Apollo, is now on sale. PARTHENON/CQ, a version customized for use by MS-DOS users, is also available. The CQ version is functionally equivalent to the workstation version, except that it imposes a limit of about 2,500 gates on the size of circuits that can be handled.

PARTHENON enables you to carry out top-down design using SFL. The logic synthesis can be optimized for the product lines of any manufacturer of Application Specific Integrated Circuits (ASICs). All you have to do is to prepare cell libraries specific to the manufacturer or to the product line. (The description language for cell libraries is provided.)

ASICs can be developed rapidly by entering a netlist (which describes the connections between elements), which is the output from PARTHENON, into the placement/routing programs of the manufacturers, and completing the subsequent processing. Field Programmable Gate Arrays (FPGAs) can be produced by entering the netlist into an FPGA mapping tool appropriate to the manufacturer. Thus, you can create your own LSI economically in a short period of time.

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